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Figure 1.  Basic schematic diagram of MTJ structure consisting of a free layer, a barrier layer, and a fixed layer.

Figure 2.  Proposed hybrid MTJ-STT/CMOS modeling framework.

Figure 3.  (a) Schematic illustration of STT-MTJ device, (b) measured and simulated variation of resistance with current of STT-MTJ, with H_ext equaling 0 Oe (the unit 1 Oe = 79.5775 A⋅m⁻¹), (c) time-dependent resistances, and (d) free layer precession 3D trajectories of the STT-MTJ device at different input currents.

Figure 4.  (a) Resistance, (b) resistance spectrum, and (c) free layer precession 3D trajectory of STNO device when the input current is −0.2 mA. (d) STNO oscillation fundamental frequency as a function of I with and without thermal noise with H_ext equaling 0 Oe, the point marked in pentagram indicating that the corresponding frequency is 1.01 GHz when the input current is −0.2 mA.

Figure 5.  (a) PCSA circuit consisting of STT-MTJ devices, three NMOS transistors and four PMOS transistors, (b) control single (SEN) and the simulated voltage results of Q_m and Q_{m_bar}.

Figure 6.  (a) Schematic diagram of two STNOs with electrical coupling, STNO oscillation frequencies as a function of (b) magnetic field applied perpendicular to the plane of free layer and (c) bias current under constant zero magnetic field (T = 0 K).