Search Advanced
2006 Volume 15 Issue 1
Article Contents
Previous Article Next Article

Ma Xiao-Hua, Hao Yue, Sun Bao-Gang, Gao Hai-Xia, Ren Hong-Xia, Zhang Jin-Cheng, Zhang Jin-Feng, Zhang Xiao-Ju, Zhang Wei-dong. 2006: Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process, Chinese Physics B, 15(1): 195-198.
Citation: Ma Xiao-Hua, Hao Yue, Sun Bao-Gang, Gao Hai-Xia, Ren Hong-Xia, Zhang Jin-Cheng, Zhang Jin-Feng, Zhang Xiao-Ju, Zhang Wei-dong. 2006: Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process, Chinese Physics B, 15(1): 195-198.
shu

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

  • Microelectronics Institute,Xidian University,Xi'an 710071,China;Key Laboratory of Ministry of Education for Wide Band-gap Semiconductor Materials and Devices,Xidian University,Xi'an 710071,China

  • Microelectronics Institute,Chinese Academy of Sciences,Beijing 100029,China

  • School of Design,Engineering and Computing,Bournemouth University,UK

  • Available Online: 30/01/2006
  • Fund Project: the National Natural Science Foundation of China (Grant 60376024)
  • N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.
  • 加载中
  • 加载中
通讯作者: 陈斌, bchen63@163.com
  • 1. 

    沈阳化工大学材料科学与工程学院 沈阳 110142

  1. 本站搜索
  2. 百度学术搜索
  3. 万方数据库搜索
  4. CNKI搜索
Export Citation
PDF
XML

Article Metrics

Article views(282) PDF downloads(0) Cited by(0)

Access History

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

  • Available Online: 30/01/2006

Abstract: N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.

    HTML

Reference (0)

Catalog

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return